SMSC LAN9312 - Manual (Page 227)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312 227 Revision 1.4 (08-19-08)
DATASHEET
3 1588 Port 0(Host MAC) TX Interrupt (1588_MII_TX_INT)
This interrupt indicates that a packet from the Host MAC to the switch fabric
matches the configured PTP packet and the 1588 clock was captured.
Note: For Port 0, receive is defined as data from the switch fabric, while
transmit is to the switch fabric.
R/WC 0b
2 1588 GPIO9 Interrupt (1588_GPIO9_INT)
This interrupt indicates that an event on GPIO9 occurred and the 1588 clock
was captured. These interrupts are configured through the
General Purpose
I/O Configuration Register (GPIO_CFG) register.
Note: As 1588 capture inputs, GPIO inputs are edge sensitive and must
be active for greater than 40 nS to be recognized as interrupt
inputs.
R/WC 0b
1 1588 GPIO8 Interrupt (1588_GPIO8_INT)
This interrupt indicates that an event on GPIO8 occurred and the 1588 clock
was captured. These interrupts are configured through the
General Purpose
I/O Configuration Register (GPIO_CFG) register.
Note: As 1588 capture inputs, GPIO inputs are edge sensitive and must
be active for greater than 40 nS to be recognized as interrupt
inputs.
R/WC 0b
0 1588 Timer Interrupt (1588_TIMER_INT)
This interrupt indicates that the 1588 clock equaled or passed the Clock
Target value in the
1588 Clock Target High-DWORD Register
(1588_CLOCK_TARGET_HI) and 1588 Clock Target Low-DWORD Register
(1588_CLOCK_TARGET_LO) .
Note: This bit is also cleared by an active edge on GPIO[9:8] if enabled.
For the clear function, GPIO inputs are edge sensitive and must be
active for greater than 40 nS to be recognized as a clear input.
Refer to
Section 13.2, "GPIO Operation," on page 162 for
additional information.
R/WC 0b
BITS DESCRIPTION TYPE DEFAULT