FUJITSU Semiconductor - Manual (Page 141)

140
■ F 2 MC-16F Family Features
• About 3 times faster version of the F 2 MC-16 (MB90700 series) with object code upward compatibility
• Various extended instructions including signed division
• Easy programming with plenty of data types, bit (1 bit), nibble (4 bits), byte (8 bits), word (16 bits), and long word
(32-bit), and 25 different addressing
• Bank and linear support of 16Mbytes large memory space makes migration
From external large memory space to single chip systems easy
• Registers
Dedicated registers
General-purpose registers: 8
×
16-bit per bank, 32 banks Max.
• Pipeline processing using 8-byte cue (minimum instruction execution time: 62.5ns/16MHz)
• Function for checking stack area in real time.
• Powerful real time processing using 8-level hardware support priority interrupts and extended intelligent I/O ser-
vice functions.
• Enhanced C language and real time operating system instructions (in SP indirect addressing, RETIQ, etc.)
• Number of basic instructions: 412
Memory space
FFFFFF H
FF0000
H
FE0000 H
020000
H
010000
H
000000 H
Bank FF
Bank FE
Bank 01
Bank 00
·
·
·
·
·
·
·
·
16MB
0000 H
0100 H
0180 H
0380
H
FFFF
H
General-purpose
register area
I/O area
Access possible
to any space PC,
DT, SP or AD
@RL access
DPR
PCB
DTB
USB
SSB
ADB
000180 H +(RP × 10 H )
→
Lower address
Upper address
16 bits
General-purpose registers AH
USP
AL Accumulator
User stack pointer
8 bits
16 bits
(RW7)
(RW6)
(RW5)
(RW4)
32 Max.




















(RL3)
(RL2)
(RL1)
(RL0)
SSP
PS
PC
System stack pointer
Processor status
Program counter
Direct page register
Program bank register
Data bank register
User stack bank register
System stack bank register
Additional data bank register
32 bits
Dedicated registers
USPCU
SSPCU
USPCL
SSPCL
User stack upper limit register
System stack upper limit register
User stack lower limit register
System stack lower limit register
R7 R6
R5 R4
R3 R2
R1 R0
RW3
RW2
RW1
RW0
16-bit Proprietary F 2 MC-16F Family
Features