FUJITSU SPARC ENTERPRISE T5220 - Manual (Page 23)

Server Features 7
Additional Feature Information
Chip-Multitheaded Processor and Memory
Technology
The UltraSPARC ® T2 multicore processor is the basis of the SPARC Enterprise T5120
and T5220 Servers. The UltraSPARC T2 processor is based on chip multithreading
(CMT) technology that is optimized for highly threaded transactional processing.
The UltraSPARC T2 processor improves throughput while using less power and
dissipating less heat than conventional processor designs.
Depending on the model purchased, the processor has four, six, or eight UltraSPARC
cores. Each core equates to a 64-bit execution pipeline capable of running eight
threads. The result is that the 8-core processor handles up to 64 active threads
concurrently.
Additional processor components, such as L1 cache, L2 cache, memory access
crossbar, memory controllers, and the I/O interface have been carefully tuned for
optimal performance.
Performance Enhancements
The SPARC Enterprise T5120 and T5220 servers running the Solaris 10 OS provide
several new performance enhancing technologies with its sun4v architecture and
multicore, multithreaded UltraSPARC T2 processor.
Some of these enhancements are:
■ A floating point unit (FPU) for each core
■ Four independent dual-channel memory controllers that use the latest fully
buffered memory technology.
■ Processor-integrated cyptographic acceleration
■ Large page optimization
■ Reduction on TLB misses
■ Optimized block copy
■ Support for 10-Gb Ethernet with the addition of XAUI cards