Intel AS/400 RISC Server - Manual (Page 348)

13800 3.7 of 4 (3) 2x4MB / 0 MB 4000 52BE n/a n/a JS22 (7998-61X)
11040 3 of 4 (2) 2x4MB / 0 MB 4000 52BE n/a n/a JS22 (7998-61X)
Processor
CPW
CPUs
L2/L3 cache
(1)
per chip
Chip Speed
MHz
Processor
Feature
Edition
Feature Server
Feature
Blade Model
Table C.4.1. IBM BladeCenter models
*Note: 1. These models have a dedicated L2 cache per processor core, and no L3 cache
2. CPW value is for a 3-core dedicated partition and a 1-core VIOS
3. CPW value is for a 3.7-core partition with shared processors and a 0.3-core VIOS partition
C.5 V5R4 Additions (July 2007)
C.5.1 IBM System i using the POWER6 processor technology
24200-172000 10800-76900 2 - 16 2x4MB / 32MB 4700 7380 7063 (3) 4924 i570 (9406-MMA)
12300-89700 5500-40100 1 - 8 2x4MB / 32MB 4700 7380 7058 (3) 4923 i570 (9406-MMA)
12300-47500 5500-21200 1 - 4 2x4MB / 32MB 4700 7380 7053 (3) 4922 i570 (9406-MMA)
45000-172000 20100-76900 4 - 16 2x4MB / 32MB 4700 7380 5462 4912 i570 (9406-MMA)
24200-89700 10800-40100 2 - 8 2x4MB / 32MB 4700 7380 5461 4911 i570 (9406-MMA)
12300-47500 5500-21200 1 - 4 2x4MB / 32MB 4700 7380 5460 4910 i570 (9406-MMA)
MCU (4)
Processor
CPW
CPU (5)
Range
L2/L3 cache (1)
per chip
Chip Speed
MHz
Processor
Feature
Edition
Feature
2
Server
Feature
Model
Table C.5.1. System i models
*Note: 1. These models have a dedicated L2 cache per processor core, and share the L3 cache
between two processor cores.
2. This is the Edition Feature for the model. This is the feature displayed when you display
the system value QPRCFEAT.
3. Capacity Backup model.
4. Projected values. See Chapter 11 for more information.
5. The range of the number of processor cores per system.
C.6 V5R4 Additions (January/May/August 2006 and January/April 2007)
C.6.1 IBM System i using the POWER5 processor technology
68400 (7) - 131K
(7) Per Processor 31500-58800 8-16 1.9/36MB 2300 NA 5890 9406-595
35800 (7) - 242K (7) 0 16000-108000 4 - 32 1.9/36MB 2300 NA 5876 (4) 9406-595
35800 (7) - 242K (7) Per Processor 16000-108000 4 - 32 1.9/36MB 2300 NA 5896 (4) 9406-595
131K (7) - 242K (7) 0 61000-108000 16 - 32 1.9/36MB 2300 NA 5871 9406-595
131K (7) - 242K
(7) Per Processor 61000-108000 16 - 32 1.9/36MB 2300 NA 5891 9406-595
242K (7) - 460K
(7) 0 108000-216000 32 - 64
(8) 1.9/36MB 2300 NA 5872 9406-595
242K (7) - 460K
(7) Per Processor 108000-216000 32 - 64
(8) 1.9/36MB 2300 NA 5892 9406-595
MCU
5250 OLTP
CPW
Processor
CPW
CPU
Range
L2/L3 cache
per CPU
(1)
Chip Speed
MHz
Accelerator
Feature
Edition
Feature
2
Model
Table C.6.1.1. System i models
IBM i 6.1 Performance Capabilities Reference - January/April/October 2008
©
Copyright IBM Corp. 2008 Appendix C CPW, CIW and MCU for System i Platform 348