Avago Technologies LSI8751D Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for LSI8751D Avago Technologies
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 314 |
| Size: | 2.39 MB |
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Document Outline
- LSI53C875/875E PCI to Ultra SCSI I/O Processor
- Chapter1 General Description
- 1.1 Package and Feature Options
- 1.2 Benefits of Ultra SCSI
- 1.3 TolerANT® Technology
- 1.4 LSI53C875 Benefits Summary
- Chapter2 Functional Description
- 2.1 SCSI Functional Description
- 2.2 Designing an Ultra SCSI System
- 2.3 Prefetching SCRIPTS Instructions
- 2.4 External Memory Interface
- 2.5 PCI Cache Mode
- 2.5.1 Load/Store Instructions
- 2.5.2 3.3 V/5 V PCI Interface
- 2.5.3 Additional Access to General Purpose Pins
- 2.5.4 JTAG Boundary Scan Testing
- 2.5.5 Big and Little Endian Support
- 2.5.6 Loopback Mode
- 2.5.7 Parity Options
- 2.5.8 DMA FIFO
- 2.5.9 SCSI Bus Interface
- 2.5.10 Select/Reselect During Selection/Reselection
- 2.5.11 Synchronous Operation
- 2.5.12 Ultra SCSI Synchronous Data Transfers
- 2.5.13 Interrupt Handling
- 2.5.14 Chained Block Moves
- 2.6 Power Management
- Chapter3 PCI Functional Description
- 3.1 PCI Addressing
- 3.2 PCI Cache Mode
- 3.3 Configuration Registers
- Chapter4 Signal Descriptions
- Figure4.1 LSI53C875 Pin Diagram
- Figure4.2 LSI53C875J Pin Diagram
- Figure4.3 LSI53C875N Pin Diagram
- Figure4.4 LSI53C875JB Pin Diagram (Top View)
- Figure4.5 LSI53C875 Functional Signal Grouping
- Table 4.4 System Signals
- Table 4.5 Address and Data Signals
- Table 4.6 Interface Control Signals
- Table 4.7 Arbitration Signals
- Table 4.8 Error Reporting Signals
- Table 4.9 SCSI SIgnals
- Table 4.10 Additional Interface Signals
- Table 4.11 External Memory Interface Signals
- Table 4.12 JTAG Signals (LSI53C875J/LSI53C875N/LSI53C875JB Only)
- 4.1 MAD Bus Programming
- Chapter5 SCSI Operating Registers
- Chapter6 Instruction Set of the I/O Processor
- 6.1 SCSI SCRIPTS
- 6.2 Block Move Instructions
- 6.3 I/O Instruction
- 6.4 Read/Write Instructions
- 6.5 Transfer Control Instructions
- 6.6 Memory Move Instructions
- 6.7 Load and Store Instructions
- Chapter7 Instruction Set of the I/O Processor
- 7.1 DC Characteristics
- Table 7.1 Absolute Maximum Stress Ratings
- Table 7.2 Operating Conditions
- Table 7.3 SCSI Signals—SD[15:0]/, SDP[1:0]/, SREQ/, SACK/
- Table 7.4 SCSI Signals—SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/
- Table 7.5 Input Signals—CLK, SCLK, GNT/, IDSEL, RST/, TESTIN, DIFFSENS, BIG_LIT/
- Table 7.6 Capacitance
- Table 7.7 Output Signals—MAC/_TESTOUT, REQ/
- Table 7.8 Output Signals—IRQ/, SDIR[15:0], SDIRP0, SDIRP1, BSYDIR, SELDIR, RSTDIR, TGS, IGS, MAS/...
- Table 7.9 Output Signal—SERR/
- Table 7.10 Bidirectional Signals—AD[31:0], C_BE[3:0], FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/...
- Table 7.11 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/, GPIO2_MAS2/, GPIO3, GPIO4
- Table 7.12 Bidirectional Signals—MAD[7:0]
- Table 7.13 Input Signals—TDI, TMS, TCK (LSI53C875J, LSI53C875JB, LSI53C875N Only)
- Table 7.14 Output Signal—TDO (LSI53C875, LSI53C875JB, LSI53C875N Only)
- 7.2 TolerANT Technology Electrical Characteristics
- 7.3 AC Characteristics
- 7.4 PCI and External Memory Interface Timing Diagrams
- 7.4.1 Target Timing
- 7.4.2 Initiator Timing
- 7.4.3 External Memory Timing
- Figure7.21 Read Cycle, Normal/Fast Memory (³ 64 Kbytes), Single Byte Access
- Figure7.22 Write Cycle, Normal/Fast Memory (³ 64 Kbytes), Single Byte Access
- Figure7.23 Read Cycle, Normal/Fast Memory (³ 64 Kbyte), Multiple Byte Access
- Figure7.24 Write Cycle, Normal/Fast Memory (³ 64 Kbyte), Multiple Byte Access
- Figure7.25 Read Cycle, Slow Memory (³ 64 Kbyte)
- Figure7.26 Write Cycle, Slow Memory (³ 64 Kbyte)
- Figure7.27 Read Cycle, Normal/Fast Memory (³ 64 Kbyte)
- Figure7.28 Write Cycle, Normal/Fast Memory (³ 64 Kbyte)
- Figure7.29 Read Cycle, Slow Memory (£ 64 Kbyte)
- Figure7.30 Write Cycle, Slow Memory (£ 64 Kbyte)
- 7.5 PCI and External Memory Interface Timing
- 7.6 SCSI Timing Diagrams
- Table 7.20 Initiator Asynchronous Send
- Figure7.31 Initiator Asynchronous Send
- Figure7.32 Initiator Asynchronous Receive
- Figure7.33 Target Asynchronous Send
- Figure7.34 Target Asynchronous Receive
- Figure7.35 Initiator and Target Synchronous Transfer
- Table 7.24 SCSI-1 Transfers (SE, 5.0 Mbytes/s)
- Table 7.25 SCSI-1 Transfers (Differential, 4.17 Mbytes/s)
- Table 7.26 SCSI-2 Fast Transfers 10.0 Mbytes/s (8-Bit Transfers) or 20.0 Mbytes/s (16-Bit Transfe...
- Table 7.27 SCSI-2 Fast Transfers 10.0 Mbytes/s (8-Bit Transfers) or 20.0 Mbytes/s (16-Bit Transfe...
- Table 7.28 Ultra SCSI SE Transfers 20.0 Mbytes/s (8-Bit Transfers) or 40.0 Mbytes/s (16-Bit Trans...
- Table 7.29 Ultra SCSI Differential Transfers 20.0 Mbytes/s (8-Bit Transfers) or 40.0Mbytes/s (16...
- 7.7 Package Drawings
- AppendixA Register Summary
- AppendixB External Memory Interface Diagram Examples
- Index
- Customer Feedback