Altera POS-PHY Level 4 IP Core Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for POS-PHY Level 4 IP Core Altera
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 142 |
| Size: | 2.74 MB |
Show table of contents
Document Outline
- DecemberPOS-PHY Level 4 IP Core User Guide
- 1. About This IP Core
- 2. Getting Started
- 3. Parameter Settings
- 4. Functional Description—Receiver
- Features
- Block Description
- Clock Structure
- Reset Structure
- Error Flagging and Handling
- Signals
- Avalon-MM Interface Register Map
- Latency Information
- 5. Functional Description—Transmitter
- 6. Testbench
- A. Start-Up Sequence
- B. Sharing PLLs for Multicore Designs
- C. Optimum Frequency for rxsys_clk
- D. Board Design
- E. Programming the SPI-4.2 Calendar via the Avalon Memory-Mapped Interface
- F. Static and Dynamic Phase Alignment
- G. Conversion from v2.2.x
- Additional Information