Altera Low Latency 100-Gbps Ethernet MAC and PHY MegaCore Function Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for Low Latency 100-Gbps Ethernet MAC and PHY MegaCore Function Altera
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 196 |
| Size: | 1.73 MB |
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Document Outline
- Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
- Contents
- 1. About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function
- 2. Getting Started
- Installation and Licensing for LL 40-100GbE IP Core for Stratix V Devices
- Installing and Licensing IP Cores
- Specifying the Low Latency 40-100GbE IP Core Parameters and Options
- IP Core Parameters
- Files Generated for Stratix V Variations
- Files Generated for Arria 10 Variations
- Integrating Your IP Core in Your Design
- Pin Assignments
- External Transceiver Reconfiguration Controller Required in Stratix V Designs
- External Transceiver PLL Required in Arria 10 Designs
- External Time-of-Day Module for Variations with 1588 PTP Feature
- Clock Requirements for 40GBASE-KR4 Variations
- External TX MAC PLL
- Placement Settings for the Low Latency 40-100GbE IP Core
- Low Latency 40-100GbE IP Core Testbenches
- Simulating the Low Latency 40‑100GbE IP Core With the Testbenches
- Compiling the Full Design and Programming the FPGA
- Initializing the IP Core
- 3. Functional Description
- High Level System Overview
- Low Latency 40-100GbE MAC and PHY Functional Description
- Low Latency 40-100GbE IP Core TX Datapath
- Low Latency 40-100GbE IP Core TX Data Bus Interfaces
- Low Latency 40-100GbE IP Core RX Datapath
- Low Latency 40-100GbE IP Core RX Data Bus Interface
- Low Latency 100GbE CAUI–4 PHY
- External Reconfiguration Controller
- External Transceiver PLL
- External TX MAC PLL
- Congestion and Flow Control Using Pause Frames
- Pause Control and Generation Interface
- Pause Control Frame Filtering
- Link Fault Signaling Interface
- Statistics Counters Interface
- 1588 Precision Time Protocol Interfaces
- PHY Status Interface
- Transceiver PHY Serial Data Interface
- Low Latency 40GBASE-KR4 IP Core Variations
- Control and Status Interface
- Arria 10 Transceiver Reconfiguration Interface
- Clocks
- Resets
- Signals
- Software Interface: Registers
- Ethernet Glossary
- 4. Debugging the 40GbE and 100GbE Link
- A. Low Latency 40-100GbE IP Core Example Project
- B. Arria 10 10GBASE-KR Registers
- C. Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v15.0
- D. Additional Information