Altera Integer Arithmetic IP Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for Integer Arithmetic IP Altera
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 157 |
| Size: | 2.13 MB |
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Document Outline
- Integer Arithmetic IP Cores User Guide
- Contents
- 1. Integer Arithmetic Megafunctions
- Design Example Files
- Installing and Licensing IP Cores
- Customizing and Generating IP Cores
- IP Catalog and Parameter Editor
- Using the Parameter Editor
- Specifying IP Core Parameters and Options
- Specifying IP Core Parameters and Options (Legacy Parameter Editors)
- Upgrading IP Cores
- Migrating IP Cores to a Different Device
- Simulating Altera IP Cores in other EDA Tools
- 2. LPM_COUNTER (Counter)
- 3. LPM_DIVIDE (Divider)
- 4. LPM_MULT (Multiplier)
- 5. ALTECC (Error Correction Code: Encoder/Decoder)
- ALTECC_ENCODER Features
- Resource Utilization and Performance
- Verilog HDL Prototype (ALTECC_ENCODER)
- Verilog HDL Prototype (ALTECC_DECODER)
- VHDL Component Declaration (ALTECC_ENCODER)
- VHDL Component Declaration (ALTECC_DECODER)
- VHDL LIBRARY_USE Declaration
- Ports (ALTECC_ENCODER)
- Ports (ALTECC_DECODER)
- Parameters (ALTECC_ENCODER)
- Parameters (ALTECC_DECODER)
- Design Example 1: ALTECC_ENCODER
- Design Example 2: ALTECC_DECODER
- 6. ALTERA_MULT_ADD (Multiply-Adder)
- 7. ALTMEMMULT (Memory-based Constant Coefficient Multiplier)
- 8. ALTMULT_ACCUM (Multiply-Accumulate)
- 9. ALTMULT_ADD (Multiply-Adder)
- 10. ALTMULT_COMPLEX (Complex Multiplier)
- Complex Multiplication
- Canonical Representation
- Conventional Representation
- Features
- Resource Utilization and Performance
- Verilog HDL Prototype
- VHDL Component Declaration
- VHDL LIBRARY_USE Declaration
- ALTMULT_COMPLEX Ports
- ALTMULT_COMPLEX Parameters
- Design Example: Multiplication of 8-bit Complex Numbers Using Canonical Representation
- Understanding the Simulation Results
- 11. ALTSQRT (Integer Square Root)
- 12. PARALLEL_ADD (Parallel Adder)
- 13. Document Revision History