Avago Technologies ACPL-339J-000E - Manual

ACPL-339J
Isolated Gate Driver Evaluation Board
User’s Manual
Quick-Start
Visual inspection is needed to ensure that the evaluation board is received in good condition. The default connections
of the evaluation board are as follows:
1. A 15 V Zener diode at D1 is provided to allow for a single DC power supply of 21.6 V ~ 30 V to be applied across V
cc2
and V
ee
. A virtual ground V
e
(at COM pin of CON2) will be generated, and it acts as the reference point at the emitter
of each IGBT. V
cc2
will then stay at 15 V above the virtual ground V
e
. R11 is needed to provide the bias current across
D1.
2. Actual IGBT can be mounted at either Q5 (for TO-220 package) or Q6 (for TO-247 package) or connected to the driver
board through short wire connections from the holes provided at Q5 or Q6.
3. S2 jumper is shorted by default to allow for the driver board to be tested without actual IGBT connection at Q5 or Q6.
Note: Once IGBT is connected at either the Q5 or Q6 location, this S2 jumper must be removed to allow for IGBT Desat
protection to be activated.
4. J1 is shorted by default, assuming that a Desat detection voltage of 8 V is needed. To reduce the Desat detection
voltage by another 1 V, this jumper can be replaced by another piece of D3 diode (BYM26E). To further reduce the
Desat detection voltage, higher VF voltage diodes can be selected to replace both D3 and J1, plus the use of higher
resistance for R4.
5. S1 is shorted by default to ground the IN1– signal. This short can be removed if IN1– cannot be grounded.
Once inspection is done, the evaluation board can be powered up in five simple steps (see Figure 1), to test either one of
the top and bottom half bridge inverter arms in simulation mode without the need of actual IGBT (or Power MOSFET).
Testing Either Arm of The Half Bridge Inverter Driver (without IGBT)
1. Solder a 10 nF capacitor across gate and emitter terminals of Q5 (to simulate actual gate capacitance of IGBT/power
MOSFET).
2. Connect a +5 V DC supply (DC supply 1) across +5 V and GND terminals of CON1.
3. Connect another DC supply (DC Supply 2 with voltage range from 21.6 V ~ 30 V) across V
cc2
(+15V) and V
ee
(-6.6 V ~
-15 V) terminals of CON2. This can be non-isolated for testing purpose.
4. Supply a 10 kHz 5 V DC pulse (at 50% duty) from a signal generator across IN1+ & IN1– pins of CON1 to simulate
microcontroller output to drive either arm of the half bridge Inverter.
5. Use a multi-channel digital oscilloscope to capture the waveforms at the following points:
a. LED signal at IN1+ pin with reference to (w.r.t.) GND.
b. Fault output for any fault signal appearing at FAULT pin w.r.t. GND.
c. V
outn
for the negative output voltage of ACPL-339J at U1 pin 11 w.r.t. V
e
(COM pin).
d. V
outp
for the positive output voltage of ACPL-339J at U1 pin 12 w.r.t. V
e
.
e. V
gmos
for the gmos output voltage of ACPL-339J at U1 pin 14 w.r.t. V
e
.
f. V
desat
for the DESAT voltage of Q5/Q6 Collector w.r.t. V
e
.
g. VgIGBT for the gate driving voltage of Q5/Q6 Gate w.r.t. V
e
.
Note: A DESAT fault can be simulated by removing the S2 Jumper.