Grass Valley 8916 - Manual (Page 23)

8916 Instruction Manual 17
Functional Description
Delay FIFO
The FIFO receives parallel data from the FPGA. The FPGA provides all
clock and control signals. The FIFO output is sent back to the FPGA.
The capacity of the FIFO is 262214 x 12 bits. A single audio sample is 48 bits
of data. With a sampling rate of 48 kHz the maximum delay of the card is
510 ms.
Transmitter/Multiplexer Circuit
The serial data, after being delayed, is routed to the Interface Transmitter
from the FPGA. The Transmitter multiplexes the channel, user, and validity
data from the receiver chip with the serial audio data from the FPGA.
Line Drivers
The line driver chip drives seven output lines. The outputs feed an RC
network that:
■ Attenuates the signal to one volt peak-to-peak
■ Limits the risetime to meet the AES specification, and
■ Creates a 75
Ω
output resistance to match the cable impedance.
Delay Adjustment Switches
There are two rotary output timing adjustment switches:
■ A fine-step adjustment switch provides sixteen 2ms timing steps
■ A coarse-step adjustment switch provides sixteen 32ms timing steps
The switches provide output timing adjustable from 2ms to 510ms with
respect to the input.
Audio Delay Control Interface
The 8916 auto delay control input consists of a one wire serial signal using
RS232 voltage levels, input on a coaxial BNC connector (Delay Input).
Delay values can range from 0 to 3FF(hex).