Sundance SMT361Q - Manual (Page 9)

Version 1.0.2 Page 9 of 24 SMT361Q User Manual
Clock settings
An on-board crystal oscillator (X2) provides the clock used for the C60, which is then
multiplied by 12 internally. (50MHz x 12 = 600MHz).
As the clock mode is set to "10" the EMIF clock is running at CPU clock/6 i.e.
100MHz.
Boot Mode
The SMT361Q is configured to boot from flash after a reset
Flash Boot
1. The DSP_A copies a bootstrap program from the first part of the flash memory
into internal program RAM starting at address 0.
2. Execution starts at address 0.
The standard bootstrap supplied with the SMT361Q then performs the following
operations:
1. All relevant C60 internal registers are set to default values;
2. The FPGA is configured from data held in flash memory and sets up the
communication ports, the global bus and the Sundance High-speed Buses.
This step must have been completed before data can be sent to the ComPorts
from external sources such as the host or other TIMs;
3. The configuration for DSP_B is sent with HPI. DSP_B then passes it on the
same way to DSP_C which pass it on the same way to DSP_D. All DSPs are
configured and waiting to boot over their ComPorts (see after).
4. A C4x-style boot loader is executed. This will continually examine the
ComPorts until data appears on one of them. The bootstrap will then load a
program in boot format from that port; the loader will not read data arriving on
other ports.
5. Finally, control is passed to the loaded program.
The delay between the release of the board reset and the FPGA configuration is
around 1s for a SMT361Q.
A typical time to wait after releasing the board reset should be in excess of this
delay, but no damage will result if any of I/Os are used before they are fully
configured. In fact, the ComPorts will just produce a not ready signal when data is
attempted to be transferred during this time, and then continue normally after the
FPGA is configured.