Sundance SMT361Q - Manual (Page 11)

Version 1.0.2 Page 11 of 24 SMT361Q User Manual
FLASH
An 8MByte flash memory is provided with direct access by the DSP_A. This device
contains boot code for the DSPs and the configuration data for the FPGA.
This is a 16-bit wide device.
The first few KBytes are used for DSP boot code.
The flash device can be re-programmed by the DSP at any time. There is a software
protection mechanism to stop most errant applications from destroying the device’s
contents.
Note that the flash memory is connected as a 16-bit device, but during a C6x boot
(internal function of the C6x) only the bottom 8 bits are used.
As the C60 only provides 20 address lines on its EMIFB, two GPIO lines (9 and 10)
are used to access this device. So the device should be seen as divided in 4x
2MBytes pages.
FLASH Paging
Selecting the visible flash memory page (4 pages of 2MBytes) involves setting up the
GPIO registers bit 9 and 10. Make sure that the setup of the other GPIO is kept
untouched as they are used for external interrupt and leds.
Virtex-II FPGA
This device, a Xilinx XC2V2000, is responsible for the provision of the SHBs,
ComPorts and the Global bus. On power-up, this device is un-configured (SRAM
based FPGA technology). During the DSP boot process, the FPGA is configured for
normal operation.
The FPGA operates at EMIF speed (100MHz).
The standard configuration for the primary FPGA uses approximately 4000 slices and
24 Block rams. The remainder can be used for additional functionality.
This FPGA provides for 4 external ComPorts.
Each DSP has 6 ComPorts. One of these is external, and the other 5 are for inter-
DSP communications.
Note that the I/Os of the FPGA are not 5V tolerant.