Tms320c6416, Dsp resources and control – Sundance SMT361Q User Manual
Page 8
Version 1.0.2
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SMT361Q User Manual
TMS320C6416
The processor will run with zero wait states from internal SRAM.
The following table shows the main DSP characteristics.
Feature C6416
DMA / McBSP / Timer
64/3/3
On-chip memory
1056k bytes
Speed 1GHz
Others UTOPIA
Viterbi and Turbo decoders
The SMT361Q implementation using this DSP provides interfaces using the EMIFs
(External Memory Interfaces A & B), timers and JTAG.
The JTAG interface is provided to enable application debugging via a suitable JTAG
controller and software. Typically, this will be a
and TI Code Composer
Studio. This is an invaluable interface that enables the application programmer to
quickly debug a ‘chain’ of processors in single or multi-processor situations.
Each DSP’s EMIFA is used to connect to the Virtex-II FPGA.
The Flash ROM is connected via DSP_A, EMIFB as a 16-bit device.
DSP resources and control
The DSP resources available to each DSP are the following:
Ressource DSP_A DSP_B DSP_C DSP_D
External
ComPort
1 1 1 1
Internal ComPort
5
5
5
5
External SHB
2
0
0
0
Global bus
1
0
0
0
Flash 1 0 0 0