Sundance SMT361Q - Manual (Page 19)

Version 1.0.2 Page 19 of 24 SMT361Q User Manual
Connector Pinouts
FPGA PROG Pin Control (JP1)
The FPGA PROG pin is used to clear the FPGA configuration.
It is to be used as a safety in case the FPGA has been programmed with a bad
bitstream that corrupts the dsp external bus and prevents which any further
programming. Removing the jumper allows the user to clear the FPGA configuration
and reprogram the FPGA. A jumper must always be fitted for proper operation.
FPGA JTAG (JP2)
The following shows the pin-outs for JP2 (FPGA) JTAG connector:
Signal Pin Pin Signal
V33 1 2 TCK
GND 3 4 TMS
TDO 5 6 TDI
TTL (JP3)
The following shows the pin-outs for JP3 TTL connector:
Signal Pin Pin Signal
V33 1 2 TTL DSP_A
TTL DSP_D 3 4 TTL DSP_C
TTL DSP_B 5 6 GND