Sundance SMT361Q - Manual (Page 3)

Version 1.0.2 Page 3 of 24 SMT361Q User Manual
Table of Contents
Revision History ....................................................................................................... 2
Contacting Sundance............................................................................................... 4
Notational Conventions ........................................................................................... 5
C60 ......................................................................................................................... 5
Register Descriptions .............................................................................................. 5
Outline Description .................................................................................................. 6
Block Diagram .......................................................................................................... 7
Architecture Description.......................................................................................... 7
TMS320C6416 ........................................................................................................... 8
DSP resources and control ..................................................................................... 8
Clock settings.......................................................................................................... 9
Boot Mode............................................................................................................... 9
EMIF Control Registers......................................................................................... 10
FLASH ..................................................................................................................... 11
FLASH Paging ...................................................................................................... 11
Virtex-II FPGA ......................................................................................................... 11
External Clock......................................................................................................... 12
Version control ....................................................................................................... 12
Reprogramming the firmware and boot code ...................................................... 12
FPGA resources ..................................................................................................... 13
ComPorts .............................................................................................................. 13
Interrupts............................................................................................................... 14
SDB ...................................................................................................................... 14
SDB Clock selection .......................................................................................... 14
Global bus............................................................................................................. 14
CONFIG & NMI ..................................................................................................... 14
Timer..................................................................................................................... 14
IIOF interrupt......................................................................................................... 14
LED ....................................................................................................................... 15
TTL pins ................................................................................................................ 15
Code Composer Studio.......................................................................................... 16