Sundance SMT791 - Manual (Page 15)

An image of the external clock divided by 8 is not available in the FPGA, like it is for
the internal clock.
All clock circuitry is implemented on the daughter card. The four clocks that enter
the FPGA are passed down from the daughter card to the main board. Additional
clocks are present on the main board and can be used to clock different parts of the
design.
The control signals names in Figure 5 correspond to the names in the firmware
implementing the demo.
The sources that select the clock source path used are:
- SelClkrsrc.vhd and SelClkrsrc_pkg.vhd.
The clock sources setups can be managed by the host of from the FPGA directly.
Both vhdl and software routines are provided to allow more flexibility.
In the default firmware implemented for the demo, the clock synthesiser is set up
by the host and the VCO/PLL is set up by the FPGA.
4.4.3 Triggers Control
One trigger is available per ADC channel.
The external trigger input is received on a MMBX, fed into a LVPECL input buffer on
the SMT391. The buffered signal is passed down as a differential LVPECL signal to
the FPGA.
The Current firmware implementation does not use the external triggers.
4.4.4 Description of the Power Supply Controls
The 3.3V, 5.0V, +12V and -12V present on the main board are passed to the
daughter card (SMT391) over the daughter card power connector.
On the daughter card the ADC requires digital 3.3V, analog 3.3V and digital 2.25V.
The 3.3V from the main board to daughter card power connector is used for the
digital 3.3V. This voltage is filtered to provide the analog 3.3V. The 2.25V is
generated by a TI low noise low dropout regulator.
The PLL + VCO require +12V, -12V and +5V.
You need to make sure that the main board’s power supply tree is setup by using
the right switch settings on the main board to provide these voltages.
The FPGA also has two pins enabling the DC/DC converters of the SMT391.
These pins are set by the FPGA once it configured and are controlling two power
switch devices on the mezzanine.
The Digital 3.3v is controlled by switch “U18” enabled with the signal
“ps3v3_pins_en” from the FPGA pin AM12".
The 2.25v regulator “U16” is enabled by signal “ps2v5_pins_en” pin “AM11”.
User Manual SMT791 Page 15 of 15 Last Edited: 12/10/2010 09:52:00