Sundance SMT791 - Manual (Page 13)

4.4 Controls Description
The control information is used to configure various components on the SMT391.
The ADC, clock generators and clock multiplexors are setup from the FPGA.
The FPGA is used to give default behaviour to the mezzanine so as to run the demo
from power-up.
For the demo to run, the mezzanine is setup as follows:
• The clock synthesiser is selected as the clock source for the ADC sampling
clock (Fs) on both channels.
• The clock synthesiser receives an output frequency value and configures
itself to generate a clock at that speed.
• The ADC auto-calibrates once the sampling clock is stable in input.
It is recommended to use the PLL+VCO for high frequencies generation and to use
the clock synthesiser for lower frequency generation or for test purposes.
The Firmware package provided supports all clock setups with “VHDL” and “C”
functions, whether the configuration happens only once at power up from the FPGA
or whether the clocks need to have their values changed during runtime, in which
case it can be done from the host.
Likewise, the ADC setup functions are provided both in “VHDL” and in “C”.
The control interfaces for the ADC and clock components are 3 wire serial
interfaces, all managed by the FPGA code.
4.4.1 ADC Controls
The FPGA set ups the ADC to provide the data to the FPGA according to the timing
diagram in figure 4.2 p.12 of the ADC User Guide:
http://www.atmel.com/dyn/resources/prod_documents/doc2153.pdf )
The other settings are left to default and can be changed if required.
The files used to set up the control words in the FPGA firmware are:
- adc_setup.vhd and adc_setup_pkg.vhd.
A software routine is also provided if the set up is to be managed by a host
application to allow more flexibility.
The ADC input clock determines the sampling rate of the ADC. The ADC buffers and
divides this clock by two or four (in the set up mentioned above) to provide an LVDS
clock for each of the de-multiplexed data channel. These two clocks are used to
clock the ADC data into the FPGA.
The ADC can be set up to provide data in a different manner than the one used in
the demo firmware. The firmware would need some modifications but we designed
User Manual SMT791 Page 13 of 13 Last Edited: 12/10/2010 09:52:00