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SMT410 User Manual V1.0
Table of Contents
1
Introduction ..................................................................................................................................... 8
2
Functional Description .................................................................................................................... 9
3
Setting Up the SMT410................................................................................................................. 10
4
Memory Map ................................................................................................................................. 11
4.1
PCI Bridge Chip Internal Register (BAR0) ........................................................................... 11
4.2
I/O Space Register Assignments (BAR1) ............................................................................ 11
4.3
Memory Space Assignments(BAR2).................................................................................... 12
5
DSP Resource Memory Map ........................................................................................................ 13
6
Shared Memory Resource ............................................................................................................ 14
7
ComPorts ...................................................................................................................................... 15
7.1
Buffered ComPort................................................................................................................. 16
8
ComPort to PCI Interface.............................................................................................................. 18
8.1
ComPort Registers (Offset 0x10, BAR1).............................................................................. 18
8.2
Control Register (Offset 0x14, BAR1) .................................................................................. 18
8.3
Status Register (Offset 0x14, BAR1 , Read-Only) ............................................................... 19
8.4
Interrupt Control Register (Offset 0x18, BAR1) ................................................................... 20
9
JTAG Controller ............................................................................................................................ 22
10
Using the SMT410 External/Internal JTAG with TI Tools. ............................................................ 24
11
Firmware Upgrades ...................................................................................................................... 25
12
Global/Local Bus Transfers, DSP <-> PCI................................................................................... 27
12.1
Mailbox Accesses................................................................................................................. 27
12.1.1
Doorbell Interrupts ....................................................................................................... 28
12.2
DSP Interrupt Control ........................................................................................................... 28
12.3
DSP To Local Aperture 0 control and Accessing................................................................. 29
12.3.1
Global bus access protocol ......................................................................................... 31
13
Interrupts ....................................................................................................................................... 34
13.1
SMT410-To-PCI Interrupts ................................................................................................... 34
13.2
PCI-To-SMT410 Interrupts ................................................................................................... 35
13.3
Interrupt Registers................................................................................................................ 35
13.3.1
PCI Interrupt Configuration Register(Offset 0x4C, BAR0) .......................................... 35
13.3.2
PCI Interrupt Status Register(Offset 0x48, BAR0) ...................................................... 37
13.3.3
Local Bus Interrupt Mask Register(Offset 0x77, BAR0).............................................. 38
13.3.4
Local Bus Interrupt Status Register(Offset 0x76, BAR0) ............................................ 39
13.3.5
PCI Mailbox WRITE/READ Interrupt Control Register(Offset: Write 0xD0, BAR0 Read
0xD2, BAR0) ................................................................................................................................. 39
13.3.6
Local Bus Mailbox WRITE/READ Interrupt Control Register(Offset: Write 0xD4, BAR0
Read 0xD6, BAR0) ....................................................................................................................... 40
