Memory map, Pci bridge chip internal register (bar0), I/o space register assignments (bar1) – Sundance SMT410 v.1.0 User Manual
Page 11: Table 2 : i/o address space map
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
4 Memory
Map
All address information is given in bytes :
4.1 PCI Bridge Chip Internal Register (BAR0)
Please see V363EPC Local Bus PCI Bridge User Manual V1.04
of internal registers.
Note: Where required, registers from the V
3
datasheet have been included.
4.2 I/O Space Register Assignments (BAR1)
In target mode, the SMT410 is accessed by a host device across the PCI bus. This
allows access to the target mode registers. The operating system or BIOS will
normally allocate a base address for the target mode registers of each SMT410.
Access to each register within the SMT410 is then specified by this base address and
the offset shown in the table below.
The I/O address space is decoded as shown in the table below.
Offset
Register(Write)
Register(Read)
Width
0x0 -
-
0x4 -
-
0x8 -
-
0x0C -
-
0x10 COMPORT_OUT COMPORT_IN
32
0x14 CONTROL
STATUS
32
0x18 INT_CONTROL
32
0x1C -
-
0x20 to 0x3F
COMPORT Configuration COMPORT
Configuration
0x24 -
-
0x40
INTREG
INTREG
16
0x80 to 0xAF
TBC Write
TBC Read
16
Table 2 : I/O address space map