Sundance SMT410 v.1.0 - Manual (Page 22)

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
9 JTAG Controller
The SMT410 has an on board Test Bus Controller (TBC). The TBC is controlled from
the PCI bus giving access to the on site TIM and/or any number of external TIMs.
The TBC is a SN74ACT8990 from Texas Instruments. Please refer to the Texas
Instruments data sheet for details of this controller. The TBC is accessed in I/O space
at the Base address + 0x80.
Test Bus
Switching
Matrix
Test Bus
Controller
PCI bridge
TIM
Site
JTAG Stacking
Connectors
J2
J1
Figure 2 : TBC Data Routing
The SMT410 can operate in two TBC modes; Master mode and Slave mode. In
Master mode, the Test Bus Controller on the SMT410 drives the JTAG scan chain
through the TIM site on the SMT410. If the site is not populated with a TIM then the
module SENSE signal is used to enable a tri-state buffer connecting the TDI and
TDO (JTAG Data In and Data Out) on the site, maintaining the integrity of the JTAG
data path. This switching is automatic. The SMT410 auto detects JTAG connections
and switches the JTAG circuitry accordingly.
When the SMT410 is configured in Slave mode, the TBC on the SMT410 is disabled,
as the TBC is assumed to be on another device connected to the SMT410.
There are two JTAG connectors (J5, J31). J31 is used when in master mode to
connect to slave devices and J5 is used in slave mode to connect master devices to