Sundance SMT498 - Manual (Page 6)

Table of Figures
Figure 1 - Block diagram of the SMT498. ............................................................................... 8
Figure 2 – Single-Size PMC card (from IEEE 1386-2001)...................................................... 8
Figure 3 – QL5064 Connection............................................................................................. 10
Figure 4 - Default FPGA Configuration ................................................................................. 12
Figure 5 – SHB Connector.................................................................................................... 13
Figure 6 – RSL Top Connector ............................................................................................. 15
Figure 7 - RSL Bottom Connector........................................................................................ 15
Figure 8 – Location of JTAG IN, OUT and DIP Switches ..................................................... 27
Figure 9 - Module Side 1 View ............................................................................................. 29
Figure 10 – Module Side 2 View ........................................................................................... 29
Figure 11 – Module Side View .............................................................................................. 29
Figure 12 - Location of the DIP Switches and the PROM ..................................................... 31
Table of Tables
Table 1 - SHB configuration Matrix ....................................................................................... 14
Table 2 – RSL Speed VS FPGA Speed Grade..................................................................... 16
Table 3 – Board Clocks......................................................................................................... 16
Table 4 – PMC P11/P12 Interface ........................................................................................ 23
Table 5 – PMC P13/P14 Interface ........................................................................................ 24
Table 6 – SHB Interface........................................................................................................ 25
Table 7 – RSL Side 1 Pinout................................................................................................. 26
Table 8 – RSL Side 2 Pinout................................................................................................. 26
Table 9 – JTAG Header Pinout............................................................................................. 27
Table 10 – Status Bits Encoding........................................................................................... 34
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