Sundance SMT387 - Manual (Page 34)

Version 1.0.3 Page 34 of 42 SMT387 User Manual
Verification Procedures
The specification (design requirements) will be tested using the following:
1) Power module test.
2) FPGA configuration using DSP and/or JTAG connector.
3) Comport transfers between a SMT376 and the SMT387.
4) SDRAM memory tests.
5) SHB connector Pins Test using SHB tester PCBs.
6) Global Bus transfers between SMT387 and SMT310Q onboard SRAM.(Not
yet implemented)
7) External clock I/O tested with scope.
8) Serial ATA disk transfers
Review Procedures
Reviews will be carried out as indicated in design quality document QCF14 and in
accordance with Sundance’s ISO9000 procedures.
Validation Procedures
The validation procedure is happening during the verification procedure.
Test that all the memories are accessible by the FPGA as well as all the
communication links.
FPGA Constraint File General Information
Since only the FF896 package type is supported on SMT387, one constraints file is
provided. Some pins will not be supported on VP7.
Ordering Information
Currently, the SMT387 is available in 2 configurations: Basic and Custom.
Basic
In the basic configuration a Virtex II Pro 20 is used and allows interfacing to ALL the
memories and ALL I/Os available on the SMT387. Basic configuration includes 16MB
of SDRAM and no ZBT SRAM.