Sundance SMT387 - Manual (Page 14)

Version 1.0.3 Page 14 of 42 SMT387 User Manual
One limitation of the DSP PCI interface is that it is incapable of byte-oriented reads or
writes. This limitation has been circumvented by implementation of this feature in the
FPGA. Refer to the description of the PCI interface in the FPGA section below.
Note: Due to a defect in the DSP PCI interface, the DSP should only be operated “at
an 18.0 or 14.8 CPU-to-PCI clock frequency ratio only (e.g., 600-MHz or 490-MHz
CPU for 33-MHz PCI).” Refer to TMS320C6414, TMS320C6415, and TMS320C6416
Digital Signal Processors Silicon Errata (SPRZ011) for more information.
Virtex FPGA
The SMT387 incorporates a Xilinx Virtex XC2VP20 FPGA (XC2VP7 or XC2VP30 are
also possible). This device controls the majority of the I/O functionality on the
module, including the Comports, SHBs, global bus, timers and interrupts.
This device requires configuring after power-up (the Virtex technology is an SRAM
based logic array). This configuration is performed by the DSP as part of the boot
process.
Two control register bits are needed for this purpose, one to put the FPGA into a
‘waiting for configuration’ state, and another to actually transfer the configuration
data.
The PROG pin (causes the FPGA to enter the non-configured state) is accessed at
address 0x6C02000X. Writing to address 0x6C020000 will assert this pin, and
address 0x6C0200001 will de-assert this pin.
The configuration data clock is accessed at address 0x6C080001. Each bit of the
FPGA’s configuration bit-stream must be serially clocked through this address.
Note: This configuration process is part of the standard boot code, and does not
need to be implemented in any user application.