Power up sequence, Adc sub-system, Input level – Sundance SMT317 User Manual
Page 8: Output codes
Version 6.1
Page 8 of 24
SMT317 User Manual
5.
Power up sequence
At power up the config CPLD waits for a bitstream to configure the FPGA.
The Virtex FPGA from Xilinx is volatile in nature, and requires reconfiguring every
time the module is powered on.
From the moment the module is powered on to the time when the FPGA is
configured:
• The ADC sampling clock is the external clock (beware to respect the
• The ADC SYNC (See
) signal is maintained high to
keep the ADCs in reset state
After the FPGA is configured the ADC controls default to the values in
Table 1: Control Register description.
6.
ADC Sub-System
It consists of 8 Analog Devices AD7723 converters. These provide an overall system
performance with an ENOB of 14 (minimum) for each of the eight channels.
All ADCs simultaneously sample using the same clock.
6.1.
Input Level
The input to the ADC module is DC coupled with a pk-pk level of 4v. This is centred
about 0v.
Vmin= -2v, Vmax= +2v.
6.2.
Output Codes
The converted samples are presented on the SDB connector as 16 bits twos
complement binary.
Code 0x8000 is equivalent to –Vmax
Code 0x0000 is equivalent to 0V
Code 0x7FFF is equivalent to +Vmax