Sundance SMT317 - Manual (Page 12)

Version 6.1 Page 12 of 24 SMT317 User Manual
10.3. Overflowed FIFOs
In the case the receiving device has a FIFO, which is becoming full, the ACK signal
on the SDB connector can be used to suspend SDB data transmission, whichever
mode is selected (continuous mode or burst mode). As soon as the ACK signal is
released the transmission continues.
Indeed when a data is written in a 511x16-bit FIFO this data is immediately read and
sent via the SDB to the DSP.
But if the ACK signal on the SDB is active the sampled data are stored in the
511x16-bit FIFO. The data are outputted on the SDB cable as soon as the ACK
signal is not active anymore.
If the 511x16-bit FIFO becomes full when the ACK signal is still active the LED1 is lit.
In order to clear the overrun the user has to clear the SDB receiver’s FIFO and send
a new control word to the SMT317.
11. FPGA
A Field Programmable Gate Array (FPGA) is used to manage the ADC data
acquisition, implement one communication ports and one Sundance Digital Bus.
11.1. Fpga configuration
The Virtex FPGA from Xilinx is volatile in nature, and requires reconfiguring every
time the module is powered on. The configuration data (bitstream) must be presented
through Comm-port 3.
The bitstream is supplied on the distribution disk as ‘fpga_smt317v2.bit’.
Please refer to the SMT6500 help file in the section FPGA type TIM configuration for
more information.
When the module is not configured, LED5 will be illuminated. Upon successful
configuration, LED5 will extinguish. (LED5 located near TIM connector.)
12. ADCs Clock Source
The sample rate of the ADCs is derived from one of two sources: either from an
external clock input or via the on-board reference.
The on-board reference clock is generated by a 37.6 MHz oscillator. The highest
ADC clock frequency generated by the on-board clock is 18.8 MHz, which can be
divided up to 16 times. See
Table 1: Control Register description
The maximum external ADC clock frequency is 19.2MHz. This should be TTL
compatible.
It is not possible to divide the external clock using the Programmable Clock Divider.