Sundance SMT317 - Manual (Page 14)

Version 6.1 Page 14 of 24 SMT317 User Manual
13.1. Programmable Clock Divider
A 4-bit divider is provided which allows generating up to 16 different clock
frequencies for the ADC clock from the on-board reference clock.
Sampling frequency = ADC Clock/16
ADC Clock Frequency = 18.8 / (Divider Value +1) (MHz)
The programmable divider on default setting is to divide by 16.
The programmable divider has no effect on an external clock.
13.2. LED 1
The LED 1 is lit when the 511x16-bit FIFO is full.
In order to clear the overrun the user has to clear the SDB receiver’s FIFO and send
a new control word to the SMT317.
13.3. Synchronization signal
It’s a pulse active high.
If the internal synchronization signal is selected (bit23=1) as soon as a control word
is received a pulse is generated internally to synchronize all the ADCs.
If the external synchronization signal is selected (bit23=0) the user has to send a
pulse active high to the SMT317 via the SYNC connector to make sure all the ADCs
are synchronized together.
13.4. Trigger
In Continuous mode:
The trigger is a level. As long as the trigger is active the data are sent to the
DSP board via the SDB.
The active level is selectable. The trigger can be active high (bit26=1) or active
low (bit26=0).
In Burst mode:
The trigger is an edge.
In the case of an internal trigger, every time a new control word is sent with
burst mode selected and internal trigger selected then a new burst mode
occurs.
In the case of an external trigger, the burst mode occurs as soon as an edge
is detected on JP2 of JMP2 (0). The trigger is edge selectable:
ƒ Bit26=1 the burst is triggered on a rising edge.
ƒ Bit26=0 the burst is triggered on a falling edge.