Sundance SMT317 - Manual (Page 11)

Version 6.1 Page 11 of 24 SMT317 User Manual
Enabling a pair of channels is done by setting any one or both of the two control bits
corresponding to the 2 channels from that pair in the control register described
further down.
Only the data corresponding to the enabled channel pairs will be output on the SDB.
On the start of a new acquisition (in continuous or burst mode) the data from the
channel pair selected with the smallest channel number is always output first.
For example, Ch0-Ch4 data is always output before Ch2-Ch6 data. Then samples
are output by increasing channel pair number for the selected channel pairs.
10. Clock selection
10.1. ADCs Sampling clock
All ADCs are sampled at the same time.
The clock source can either be the onboard oscillator or an external clock.
Therefore, the sampling frequency is either given by the clock divider setting for the
onboard clock or by the external clock (the external clock is not affected by the clock
divider setting).
10.2. SDB output clock
For firmware versions released before 01/09/2005, the SMT317 module allows for
the SDB word rate to be set to either 50 or 100MHz as set by JMP2: SDB Clock
speed select.
A lower word rate may be needed when the receiving device is not able to sustain
the faster transfer speed.
In firmware versions released after 01/09/2005, the SDB clock is no more selectable
and the samples are output at a default 50Mhz clock frequency, which can easily
sustain the data rate required by the ADC data.
If the SDB data transmission is not suspended by the ACK signal and that there are
samples buffered in the SMT317 FIFO, the samples are output at the SDB output
clock frequency.