Sensoray 425 - Manual (Page 8)

Sensoray Model 425 Instruction Manual Page 6
Encoder Interface
Overview
Three counter channels reside on the 425. Each
channel is optimized for incremental encoders by
providing the following elements and features:
• Input buffers interface directly to TTL, CMOS, or
differential RS422 signals.
• Decoder logic detects and converts encoder edges into
clock and direction signals.
• 24-bit up/down counter tracks encoder position without
resorting to multiple counter channels.
• Mode register selects internal or external clock source,
clock multiplier and count direction.
• Index input auto-resets counter when armed.
• Programmable interrupt on index or rollover.
• 5 Volt encoder power available at encoder connector.
Additional elements are shared by all counter
channels:
• Holding register for reading counter contents.
• Preload register for initializing counter contents.
Index Inputs
Each counter channel has a dedicated “Index” input
signal and programmable arming register. A counter
is reset to zero when its index is asserted and armed.
Use of the Index signal is optional. If you are not
using the Index input of an encoder channel, simply
leave the corresponding input signals disconnected.
Phase Inputs
Each counter channel has two clock input phases
named “A” and “B.” Depending on the application,
one or both of these signals may be connected to an
encoder.
If both phases are used, they are assumed to be
quadrature encoded, meaning that they are 90
degrees out of phase. In this case, counters will count
both up and down based on the timing relationship of
the two phase inputs.
If only one phase is used, the input is said to be
single-phase. In this case, counter channels will
count either up or down, but not both. This
configuration is typically used to count pulses from
devices that produce a single clock output.
Quadrature encoders have advantages over single-
phase encoders. Counters will not accumulate errors
when an encoder changes direction or dithers about a
state transition boundary. Also, it is possible to
increase encoder resolution by clocking the counters
at a multiple of the single-phase clock rate.
Reset
Hardware or software reset of the 425 will zero all
counters and the Mode, Holding and Preload
registers. Counting is inhibited during the reset pulse
and subsequent fault condition.
Decode
Logic
Up/Down
Counter
D
a
ta
S
e
le
c
to
r
Timing &
Control
Holding
Register
Encoder
Inputs
To
Host
Encoder Interface Block Diagram
Up/Down
Counter
Input
Up/Down
Counter
Preload
Register
Mode
Registers
Decode
Logic
Decode
Logic
Buffer
Input
Buffer
Input
Buffer