Sensoray 425 - Manual (Page 16)

Sensoray Model 425 Instruction Manual Page 14
D/A Interface
DAC
DAC0LSB
8-bit Register
DAC0MSB
4-bit Register
12-bit
Output
Register
DAC Enable
Register
CMOS
Switch
E
Analog
Output
Local
Data
Bus
G
DAC Channel 0
(1 of 4 channels shown)
LDAC
E
G DAC
Channel 1
E
G DAC
Channel 2
E
G DAC
Channel 3
D/A Subsystem Block Diagram
EDAC
DAC Enable Register
Each DAC channel consists of a low-byte/high-
nibble bus register pair, 12-bit output register, 12-bit
D/A converter, and CMOS switch.
All four CMOS switches are enabled by the one-bit
DAC Enable Register. When enabled, the CMOS
switches connect all four DAC outputs to 40-pin
header P2. When disabled, all DAC output signals at
P2 are pulled down to zero volts.
A control strobe — LDAC — simultaneously
transfers data from the four bus register pairs to their
corresponding 12-bit output registers. DAC output
ranges are fixed at 0 to +10 volts.
Following a reset, all four 12-bit output registers
contain indeterminate values. To ensure orderly
startup, the DAC Enable Register turns off all CMOS
switches to prevent random DAC voltages from
reaching the analog I/O connector. The DAC Enable Register — which is automatically
cleared by a reset — is programmed by writing to the
General Control port with bit 11 set:
V — enables (1) or disables (0) all DAC outputs.
General Control Port (base + 40, write only) :
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
V 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0