Sensoray 526 - Manual (Page 24)

24
Interrupt Enable Register
0x0C
Bits Type Default Description
[15] WO 0 DIO7 interrupt enable.
[14] WO 0 DIO6 interrupt enable.
[13] WO 0 DIO5 interrupt enable.
[12] WO 0 DIO4 interrupt enable.
[11] WO 0 DIO3 interrupt enable.
[10] WO 0 DIO2 interrupt enable.
[9] WO 0 DIO1 interrupt enable.
[8] WO 0 DIO0 interrupt enable.
[7] UU X Reserved.
[6] WO 0 Counter 0 interrupt enable.
[5] WO 0 Counter 1 interrupt enable.
[4] WO 0 Counter 2 interrupt enable.
[3] WO 0 Counter 3 interrupt enable.
[2] WO 0 ADC interrupt enable.
[1] WO 0 DAC interrupt enable.
[0] WO 0 Timer interrupt enable.
Interrupt Status Register
0x0E
Bits Type Default Description
[15] RR 0 DIO7 interrupt status.
[14] RR 0 DIO6 interrupt status.
[13] RR 0 DIO5 interrupt status.
[12] RR 0 DIO4 interrupt status.
[11] RR 0 DIO3 interrupt status.
[10] RR 0 DIO2 interrupt status.
[9] RR 0 DIO1 interrupt status.
[8] RR 0 DIO0 interrupt status.
[7] RR 0 EEPROM interface status (status only, no interrupt).
[6] RR 0 Counter 0 interrupt status. Note 1.
[5] RR 0 Counter 1 interrupt status. Note 1.
[4] RR 0 Counter 2 interrupt status. Note 1.
[3] RR 0 Counter 3 interrupt status. Note 1.
[2] RR 0 ADC interrupt status.
[1] RR 0 DAC interrupt status.
[0] RR 0 Timer interrupt status.
Notes:
1.
This interrupt can be generated by multiple sources. Detection of the exact interrupt source
is possible through the individual interrupt status bits in the corresponding counter status
register. Those bits have to be reset as well after an interrupt occurs to enable subsequent
interrupt detection.