Foxconn 761GXM2MA-KRS2H User Manual
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Chapter 3 BIOS Description
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Write to Read Command Delay
It is used to set minimum Write-to-read delay when both access the same
chip selt.
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DIMM0/1/2/3 A/R ROW Cycle Time
This item is uased to set the minimum time from an auto-refresh command to
an active command or another auto-refresh command.
v
Write Recovery Time
It measures from the last data to precharge when the last write datum is
safely registered by the DRAM.(write can go back-to-back)
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Read to precharge Time
This item is uased to set the read CAS# to precharge time.
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Row Cycle Time
This item is used to set the time RAS#-Active to RAS#-Active or auto refresh of
the same bank.
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RAS#-active to CAS#-RW delay
This item is used to set the RAS# to CAS# delay for a read write
command to the same bank.
v
RAS#-to-RAS# delay
This item is used to set the active-to-active delay of different banks.
v
Row Precharge Time
This item controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If insufficient time is allowed for the RAS to accumuate
its charge befor DRAM refresh, refreshing may be incomplete andDRAM may
fail to retain data.This item applies only when synchronous DRAM is installed
in the system.
v
Minmum RAS# Active Time
This item is used to set the minimum RAS# active time.
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