Altera Stratix IV GX FPGA - Manual (Page 53)

Chapter : A–5
Restoring the MAX II CPLD to the Factory Settings
March 2014 Altera Corporation Stratix IV GX FPGA Development Kit User Guide
11. Click Start to download the selected configuration file to the FPGA. Configuration
is complete when the progress bar reaches 100%. The CONF DONE LED (D5) and
the eight lower user LEDs (D16-D23) illuminate indicating the flash memory
device is now restored with the factory contents.
12. Cycle the POWER switch (SW1) off then on to load and run the restored factory
design.
13. The restore script cannot restore the board’s MAC address automatically. In the
Nios II command shell, type the following Nios II EDS command:
nios2-terminal
r
14. Follow the instructions in the terminal window to generate a unique MAC
address.
f To ensure that you have the most up-to-date factory restore files and information
about this product, refer to the
Stratix IV GX FPGA Development Kit page of the
Altera website.
Restoring the MAX II CPLD to the Factory Settings
This section describes how to restore the original factory contents to the MAX II CPLD
on the FPGA development board. Make sure you have the Nios II EDS installed, and
perform the following instructions:
1. Set the board switches to the factory default settings described in “Factory Default
Switch Settings” on page 4–2 .
1 Setting DIP switch SW6.1 to the off position includes the MAX II device in
the JTAG chain.
2. Launch the Quartus II Programmer.
3. Click Auto Detect.
4. Click Add File and select
dir>\kits\stratixIVGX_4sgx230_fpga\factory_recovery\max2.pof.
5. Turn on the Program/Configure option for the added file.
6. Click Start to download the selected configuration file to the MAX II CPLD.
Configuration is complete when the progress bar reaches 100%.
f
To ensure that you have the most up-to-date factory restore files and information
about this product, refer to the
Stratix IV GX FPGA Development Kit page of the
Altera website.