Altera Reed-Solomon II MegaCore Function User Manual
Page 7

Device
Parameters
ALM
Memory
Registers
fMAX
(MHz)
Type
Check
Symbols
Bits Per
Symbol
Bits Per
Check
Symbol
M10K
M20K
Primary Secondary
Stratix V Erasures
decoder
16
8
204
1,648 --
1
1,765
423
367
Stratix V Erasures
variable
decoder
16
8
204
1,664 --
1
1,802
405
368
Stratix V Full
error
decoder
16
8
204
955
--
1
987
252
424
Stratix V Split
error
decoder
16
8
204
969
--
1
1,003
248
424
Stratix V Standard
decoder
large
32
8
255
1,624 --
1
1,749
432
404
Stratix V Standard
decoder
medium
16
8
204
939
--
1
972
281
410
Stratix V standard
decoder
small
6
4
15
197
--
1
272
52
525
Stratix V Standard
encoder
16
8
204
87
--
0
164
0
610
Stratix V Variable
decoder
16
8
204
966
--
1
1,017
270
409
Stratix V Variable
encoder
large
32
8
204
902
--
0
299
0
397
Stratix V Variable
encoder
small
16
8
204
435
--
0
169
0
434
UG-01090
2015.05.01
Reed-Solomon II IP Core Performance and Resource Utilization
1-5
About the Reed-Solomon II IP Core
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)