About the reed-solomon ii ip core, Altera dsp ip core features, Reed-solomon ii ip core features – Altera Reed-Solomon II MegaCore Function User Manual
Page 3: Dsp ip core device family support, About the reed-solomon ii ip core -1, Altera dsp ip core features -1, Reed-solomon ii ip core features -1, Dsp ip core device family support -1
About the Reed-Solomon II IP Core
1
2015.05.01
UG-01090
Altera DSP IP Core Features
• Avalon
®
Streaming (Avalon-ST) interfaces
• DSP Builder ready
• Testbenches to verify the IP core
• IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
Reed-Solomon II IP Core Features
• High-performance encoder or decoder for error detection and correction:
• • Fully parameterizable:
• Number of channels
• Number of bits per symbol
• Number of symbols per codeword
• Number of check symbols per codeword
• Field polynomial
• Erasures-supporting decoder—-the decoder can correct symbol errors up to the number of check
symbols, if you give the location of the errors to the decoder
• Error symbol output—the decoder provides the error values
• Bit error output—either split count or full count
• Multiple channels for resource sharing
DSP IP Core Device Family Support
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