Starting the nios ii ide from sopc builder – Altera Nios II User Manual
Page 17

Altera Corporation
1–9
May 2007
Nios II Development Kit Getting Started User Guide
Getting Started
5.
Click Start.
Upon download success, the Messages window will display “Info:
successfully performed operation(s).” If you do not see this message,
check your cable connections and the Quartus II Programmer
hardware setup.
Starting the Nios II IDE from SOPC Builder
Now that you have configured the FPGA with a Nios II system, you can
proceed to the Nios II IDE to download software to the processor.
To start the Nios II IDE, perform the following steps:
1.
On the Tools menu in the Quartus II software, click SOPC Builder.
2.
When the SOPC Builder window opens, click on the System
Generation
tab.
3.
Click Nios II IDE to start the Nios II IDE. See
Figure 1–2
.
1
In the future, you can launch the Nios II IDE directly
without running the Quartus II software. On the Windows
Start menu point to All Programs, Altera, Nios II EDS
<version>, and then click Nios II <version> IDE.
Figure 1–2. Starting the Nios II IDE from SOPC Builder
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)