Altera MAX V CPLD - Manual (Page 16)

5–2 Chapter 5: Board Test System
Using the Board Test System
MAX V CPLD Development Kit User Guide January 2011 Altera Corporation
A GUI appears, displaying the application tab that corresponds to the design running
in the CPLD.
Using the Board Test System
This section describes each control in the Board Test System application.
The Config Menu
Each design example tests a different functionality that corresponds to one or more
application tabs. Use the Config menu to select the design you want to use.
Figure 5–1
shows the Config menu.
To configure the CPLD with a test system design, on the Config menu, click the
configure command that corresponds to the functionality you wish to test.
1
While the configuration is running, a progress bar displays. A message shows when
the configuration is completed.
The GPIO Tab
The GPIO tab allows you to interact with all the general purpose user I/O
components on your board.
1 The MAX V CPLD Development Kit includes three designs examples for the GPIO
tab (
Figure 5–1 ):
■ BTS General (VAR_VCCIO = 3.3V) runs when I/O voltage is set to 3.3 V (Bank 2).
■ BTS General (VAR_VCCIO = 2.5V) runs when I/O voltage is set to 2.5 V (Bank 2).
■ BTS General (VAR_VCCIO = 1.8V) runs when I/O voltage is set to 1.8 V (Bank 2).
Figure 5–1. The Config Menu