Altera Arria II GX FPGA - Manual (Page 37)

Chapter 6: Board Test System 6–17
The Power Monitor
July 2010 Altera Corporation Arria II GX FPGA Development Kit, 6G Edition User Guide
The Power Monitor communicates with the MAX II device on the board through the
JTAG bus. A power monitor circuit attached to the MAX II device allows you to
measure the power that the Arria II GX FPGA device is consuming regardless of the
design currently running.
Figure 6–8 shows the Power Monitor.
The following sections describe the Power Monitor controls.
General Information
The General information controls display the following information about the
MAX II device:
■ MAX II version —Indicates the version of MAX II code currently running on the
board. The MAX II code resides in the dir>\kits\arriaIIGX_2agx260_fpga\factory_recovery and dir>\kits\arriaIIGX_2agx260_fpga\examples\max2 directories. Newer revisions
of this code might be available on the
Arria II GX FPGA Development Kit, 6G
Edition page of the Altera website.
■ Power rail —Selects the power rail to measure. After selecting the desired rail, click
Reset to refresh the screen with new board readings.
Figure 6–8. The Power Monitor