Jtag bst architecture, Jtag pins, Jtag circuitry functional model – Altera MAX 10 JTAG User Manual
Page 4: Jtag bst architecture -1, Jtag pins -1, Jtag circuitry functional model -1
JTAG BST Architecture
2
2015.05.04
UG-M10JTAG
MAX 10 JTAG interface uses four pins,
TDI
,
TDO
,
TMS
, and
TCK
.
JTAG Pins
Table 2-1: JTAG Pin Descriptions
Pin
Function
Description
TDI
Serial input pin for:
• instructions
• test data
• programming data
•
TDI
is sampled on the rising edge of
TCK
•
TDI
pins have internal weak pull-up resistors.
TDO
Serial output pin for:
• instructions
• test data
• programming data
•
TDO
is sampled on the falling edge of
TCK
• The pin is tri-stated if data is not being
shifted out of the device.
TMS
Input pin that provides the control
signal to determine the transitions of
the TAP controller state machine.
•
TMS
is sampled on the rising edge of
TCK
•
TMS
pins have internal weak pull-up resistors.
TCK
The clock input to the BST circuitry.
—
All the JTAG pins are powered by the V
CCIO
1B. In JTAG mode, the I/O pins support the LVTTL/
LVCMOS 3.3-1.5V standards.
JTAG Circuitry Functional Model
The JTAG BST circuitry requires the following registers:
• Instruction register—determines which action to perform and which data register to access.
• Bypass register (1-bit long data register)—provides a minimum-length serial path between the
TDI
and
TDO
pins.
• Boundary-scan register—shift register composed of all the BSCs of the device.
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