ADLINK aTCA-6250 - Manual (Page 20)

20
3.2.3 GPIO List
The following table summarizes GPIO usage on the Intel® C604 PCH
Control / Status Signal GPIO DIR Description
HOT SWAP LED J22 Output Blue Hot Swap LED Control
OOS_LED C9 Output LED1
BOOT _STATUS_LED C16 Output LED2
IPMC_PAYLOAD_PWR H17 Output LED3
RMII_TXDO0 AA5 Output RMII transmit data 0
RMII_TXDO1 W5 Output RMII transmit data 1
RMII_TX_ENO Y4 Output RMII transmit enable
SPI0_nSS Y20 Output SPI slave select
SPI0_DO U17 Output SPI data output
SPI0_SCK W19 Output SPI clock
IPMB BUS A ENABLE C21 Output IPMB Bus A Enable control
IPMB BUS B ENABLE J20 Output IPMB Bus B Enable control
HA7 F1 Input Hardware Address Input 7
HA6 G3 Input Hardware Address Input 6
HA5 F3 Input Hardware Address Input 5
HA4 B9 Input Hardware Address Input 4
HA3 B12 Input Hardware Address Input 3
HA2 A5 Input Hardware Address Input 2
HA1 D3 Input Hardware Address Input 1
HA0 B17 Input Hardware Address Input 0
HSWITCH A8 Input Handle Switch
SPI0_DI V18 Input SPI data input
ADC_PP_3V3 V9 Input Payload voltage (3.3V)
ADC_PP_1V5 AA8 Input Payload voltage (1.5V)
ADC_PP_5V AB8 Input Payload voltage (5V)
RMII_REF_CLK T6 Input RMII reference clock
RMII_CRS_DV W4 Input RMII carrier sense / receive data valid
RMII_RXD0 V5 Input RMII receive data 0
RMII_RXD1 U5 Input RMII receive data 1
SOL_SMB_nALERT D12 Input SOL SMBus ALERT
IPMB BUS A READY A9 Input IPMB Bus A Ready signal.
IPMB BUS B READY B14 Input IPMB Bus B Ready signal.
IPMB BUS A SCL U21 InOut IPMB Bus A Serial Data Line signal
IPMB BUS A SDA V21 InOut IPMB Bus A Serial Clock signal
IPMB BUS B SCL U20 InOut IPMB Bus B Serial Data Line signal
IPMB BUS B SDA V22 InOut IPMB Bus B Serial Clock signal
MO_SCL V1 InOut Master-onlyI2C Serial Clock signal
MO_SDA R3 InOut Master-onlyI2C Serial Clock signal
SOL_SMB_SCL W1 InOut SOL SMBus clock
SOL_SMB_SDA Y1 InOut SOL SMBus data