ADLINK PXIe-9529 - Manual (Page 36)

26 Operations
The three internal timing signals can be routed to the PXI trigger
bus through software drivers. Physically, signal routing is accom-
plished in the FPGA, with cards connected together through the
PXI trigger bus achieving synchronization on the three timing sig-
nals, as follows.
3.6.1 SSI_TIMEBASE
As output, the SSI_TIMEBASE signal transmits the onboard ADC
timebase through the PXI trigger bus. As input, the PXIe-9529
accepts the SSI_TIMEBASE signal as the source of the timebase.
3.6.2 SSI_SYNC_START
Before a SSI master issues SSI_TRIG to other SSI slaves,
SSI_SYNC_START is first asserted by the master card, synchro-
nizing all on-chip ADCs in both SSI Master and SSI Slave mod-
ules.
3.6.3 SSI_TRIG
As output, the SSI_TRIG signal reflects the trigger event signal in
an acquisition sequence. As input, the PXIe-9529 accepts the
SSI_TRIG signal as the trigger event source. The signal is config-
ured in the rising edge-detection mode, with minimum pulse width
8ns.
NOTE: NOTE:
Different signals cannot be routed onto the same trigger bus
line.