5 adc timing control, 1 timebase, Adc timing control – ADLINK PXIe-9529 User Manual

Page 33: Timebase, Figure 3-8, Re-trigger mode acquisition, Figure 3-9, Timebase architecture, Figure 3-8: re-trigger mode acquisition, Figure 3-9: timebase architecture

Operations

PXIe-9529

one clock period of PCIe CLK. After the initial setup, no addi-
tional software intervention is required.

Figure 3-8: Re-Trigger Mode Acquisition

3.5 ADC Timing Control

3.5.1

Timebase

Figure 3-9: Timebase Architecture

An onboard timebase clock drives the sigma-delta ADC, with fre-

quency exceeding the sample rate and produced by a PLL chip,
with output frequency programmable to superior resolution. The
PXIe- 9529 accepts the external 10MHz and 100MHz clocks from
the PXI Express backplane for improved synchronization between
modules.

Time

Operation

start

Trigger

Data

1st Trigger Event Occurs

N samples

2nd Trigger Event Occurs

8-t

o-1 MUX

Timeb

ase Clock Mux

I I

terf

ace

PXI Trigger Bus[0:7]

PXIe_CLK100

PXI I

rfa

PXI Trigger Bus[0:7]

PXI_CLK10

Onboard

Oscillator

10M

ADC0_CLK

ADC1_CLK

FPGA_MCLK

1-t

o-8 MUX

1-to-4 Clock

Buf

fer &

PLL

SYNC_CLK