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Logic block diagram (cy7c1413jv18), Logic block diagram (cy7c1415jv18) – Cypress CY7C1415JV18 User Manual

Page 3

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CY7C1411JV18, CY7C1426JV18

CY7C1413JV18, CY7C1415JV18

Document Number: 001-12557 Rev. *C

Page 3 of 28

Logic Block Diagram (CY7C1413JV18)

Logic Block Diagram (CY7C1415JV18)

CLK

A

(18:0)

Gen.

K

K

Control

Logic

Address

Register

D

[17:0]

Read Add. D

e

cod

e

Read Data Reg.

RPS

WPS

Control

Logic

Address

Register

Reg.

Reg.

Reg.

36

19

72

18

BWS

[1:0]

V

REF

W

rite Add. De

code

Write

Reg

36

A

(18:0)

19

18

CQ

CQ

DOFF

Q

[17:0]

18

18

18

Write

Reg

Write

Reg

Write

Reg

C

C

5

12K x 18

A

rray

5

12K x 18

A

rray

5

12K x 18

A

rray

5

12K x 18

A

rray

18

25
6K x 36 Arra

y

CLK

A

(17:0)

Gen.

K

K

Control

Logic

Address

Register

D

[35:0]

Read Add.

Deco

de

Read Data Reg.

RPS

WPS

Control

Logic

Address

Register

Reg.

Reg.

Reg.

72

18

144

36

BWS

[3:0]

V

REF

W

rite Add. D

e

cod

e

Write

Reg

72

A

(17:0)

18

25
6K x 36 Arra

y

25
6K x 36 Arra

y

25
6K x 36 Arra

y

36

CQ

CQ

DOFF

Q

[35:0]

36

36

36

Write

Reg

Write

Reg

Write

Reg

C

C

36

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