Cypress CY7C140 - Manual (Page 7)

CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
Document #: 38-06002 Rev. *E Page 7 of 19
Busy/Interrupt Timing
t
BLA
BUSY LOW from Address Match 15 20 20 ns
t
BHA
BUSY HIGH from Address Mismatch [17] 15 20 20 ns
t
BLC
BUSY LOW from CE LOW 15 20 20 ns
t
BHC
BUSY HIGH from CE HIGH
[17]
15 20 20 ns
t
PS
Port Set Up for Priority 5 5 5 ns
t
WB
[18]
R/W LOW after BUSY LOW 0 0 0 ns
t
WH
R/W HIGH after BUSY HIGH 13 20 30 ns
t
BDD
BUSY HIGH to Valid Data 15 25 30 ns
t
DDD
Write Data Valid to Read Data Valid Note 19 Note 19 Note 19 ns
t
WDD
Write Pulse to Data Delay Note 19 Note 19 Note 19 ns
Interrupt Timing
t
WINS
R/W to INTERRUPT Set Time 15 25 25 ns
t
EINS
CE to INTERRUPT Set Time 15 25 25 ns
t
INS
Address to INTERRUPT Set Time 15 25 25 ns
t
OINR
OE to INTERRUPT Reset Time
[17]
15 25 25 ns
t
EINR
CE to INTERRUPT Reset Time
[17]
15 25 25 ns
t
INR
Address to INTERRUPT Reset Time
[17]
15 25 25 ns
Shaded areas contain preliminary information.
Switching Characteristics Over the Operating Range [7, 12] (continued)
Parameter Description
7C131-15
[4]
7C131A-15
7C141-15
7C130-25
[4]
7C131-25
7C140-25
7C141-25
7C130-30
7C130A-30
7C131-30
7C140-30
7C141-30
Unit
Min Max Min Max Min Max
Notes
17. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
18. CY7C140/CY7C141 only.
19. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address is toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
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