Cypress Perform STK16C88-3 - Manual (Page 3)

STK16C88-3
Document Number: 001-50594 Rev. ** Page 3 of 14
Device Operation
The AutoStore+ STK16C88-3 is a fast 32K x 8 SRAM that does
not lose its data on power down. The data is preserved in integral
QuantumTrap non-volatile storage elements when power is lost.
Automatic STORE on power down and automatic RECALL on
power up guarantee data integrity without the use of batteries.
SRAM Read
The STK16C88-3 performs a READ cycle whenever CE and OE
are LOW while WE is HIGH. The address specified on pins A
0–14
determines the 32,768 data bytes accessed. When the READ is
initiated by an address transition, the outputs are valid after a
delay of t
AA
(READ cycle 1). If the READ is initiated by CE or OE,
the outputs are valid at t
ACE
or at t
DOE
, whichever is later (READ
cycle 2). The data outputs repeatedly respond to address
changes within the t
AA
access time without the need for transi-
tions on any control input pins, and remains valid until another
address change or until CE or OE is brought HIGH.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW.
The address inputs must be stable prior to entering the WRITE
cycle and must remain stable until either CE or WE goes HIGH
at the end of the cycle. The data on the common IO pins DQ
0–7
are written into the memory if it has valid t
SD
, before the end of
a WE controlled WRITE or before the end of an CE controlled
WRITE. Keep OE HIGH during the entire WRITE cycle to avoid
data bus contention on common IO lines. If OE is left LOW,
internal circuitry turns off the output buffers t
HZWE
after WE goes
LOW.
AutoStore+ Operation
The STK16C88-3’s automatic STORE on power down is com-
pletely transparent to the system. The STORE initiation takes
less than 500 ns when power is lost (V
CC SWITCH
) at which point
the part depends only on its internal capacitor for STORE com-
pletion.
If the power supply drops faster than 20
μs/volt before Vcc
reaches Vswitch, then a 2.2 ohm resistor should be inserted
between Vcc and the system supply to avoid a momentary
excess of current between Vcc and internal capacitor.
In order to prevent unneeded STORE operations, automatic
STOREs are ignored unless at least one WRITE operation has
taken place since the most recent STORE or RECALL cycle.
Software initiated STORE cycles are performed regardless of
whether or not a WRITE operation has taken place.
Hardware RECALL (Power Up)
During power up or after any low power condition (V
CC RESET
),
an internal RECALL request is latched. When V
CC
once again
exceeds the sense voltage of V
SWITCH
, a RECALL cycle is
automatically initiated and takes t
HRECALL
to complete.
If the STK16C88-3 is in a WRITE state at the end of power up
RECALL, the SRAM data is corrupted. To help avoid this
situation, a 10 Kohm resistor is connected either between WE
and system V
CC
or between CE and system V
CC
.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The STK16C88-3 software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence is performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
The software sequence is clocked with CE controlled READs.
When the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
READ cycles and not WRITE cycles are used in the sequence.
It is not necessary that OE is LOW for a valid sequence. After the
t
STORE
cycle time is fulfilled, the SRAM is again activated for
READ and WRITE operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations is
performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the t
RECALL
cycle time, the SRAM is once
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.
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