Application example, Truth table, Write cycle descriptions – Cypress CY7C1292DV18 User Manual
Page 7
CY7C1292DV18
CY7C1294DV18
Document #: 001-00350 Rev. *A
Page 7 of 23
Application Example
[1]
Truth Table
[2, 3, 4, 5, 6, 7]
Operation
K
RPS
WPS
DQ
DQ
Write Cycle:
Load address on the rising edge of K clock; input write
data on K and K rising edges.
L-H
X
L
D(A + 0) at K(t)
↑
D(A + 1) at K(t)
↑
Read Cycle:
Load address on the rising edge of K clock; wait one
and a half cycle; read data on C and C rising edges.
L-H
L
X
Q(A + 0) at C(t + 1)
↑ Q(A + 1) at C(t + 2) ↑
NOP: No Operation
L-H
H
H
D = X,
Q = High-Z
D = X,
Q = High-Z
Standby: Clock Stopped
Stopped
X
X
Previous State
Previous State
Write Cycle Descriptions
(CY7C1292DV18)
[2, 8]
BWS
0
BWS
1
K
K
Comments
L
L
L-H
–
During the Data portion of a Write sequence
: both bytes (D
[17:0]
) are written into the device.
L
L
–
L-H During the Data portion of a Write sequence
: both bytes (D
[17:0]
) are written into the device.
L
H
L-H
–
During the Data portion of a Write sequence
: only the lower byte (D
[8:0]
) is written into the
device. D
[17:9]
will remain unaltered.
L
H
–
L-H During the Data portion of a Write sequence
: only the lower byte (D
[8:0]
) is written into the
device. D
[17:9]
will remain unaltered.
H
L
L-H
–
During the Data portion of a Write sequence
: only the upper byte (D
[17:9]
) is written into the
device. D
[8:0]
will remain unaltered.
H
L
–
L-H During the Data portion of a Write sequence
: only the upper byte (D
[17:9]
) is written into the
device. D
[8:0]
will remain unaltered.
H
H
L-H
–
No data is written into the devices during this portion of a Write operation.
H
H
–
L-H No data is written into the devices during this portion of a Write operation.
Notes:
1. The above application shows four QDR-II being used.
2. X = “Don't Care,” H = Logic HIGH, L= Logic LOW,
↑
represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS
0
, NWS
1
, BWS
0
, BWS
1
, BWS
2
and BWS
3
can be altered on different
portions of a Write cycle, as long as the set-up and hold requirements are achieved.
Vt = Vddq/2
C C#
D
A
K
C C#
D
A
K
BUS
MASTER
(CPU
or
ASIC)
SRAM #1
SRAM #4
DATA IN
DATA OUT
Address
RPS#
WPS#
BWS#
Source K
Source K#
Delayed K
Delayed K#
R = 50
οηµσ
R = 250
οηµσ
R = 250
οηµσ
R
P
S
#
W
P
S
#
B
W
S
#
R
P
S
#
W
P
S
#
B
W
S
#
Vt
Vt
Vt
R
R
R
ZQ
CQ/CQ#
Q
K#
ZQ
CQ/CQ#
Q
K#
CLKIN/CLKIN#