Switching characteristics – Cypress CY7C1231H User Manual
Page 8
CY7C1231H
Document #: 001-00207 Rev. *B
Page 8 of 12
Switching Characteristics
Over the Operating Range
[12, 13]
Parameter
Description
-133
Unit
Min.
Max.
t
POWER
V
DD
(Typical) to the first Access
[14]
1
ms
Clock
t
CYC
Clock Cycle Time
7.5
ns
t
CH
Clock HIGH
2.5
ns
t
CL
Clock LOW
2.5
ns
Output Times
t
CDV
Data Output Valid after CLK Rise
6.5
ns
t
DOH
Data Output Hold after CLK Rise
2.0
ns
t
CLZ
Clock to Low-Z
[15, 16, 17]
0
ns
t
CHZ
Clock to High-Z
[15, 16, 17]
3.5
ns
t
OEV
OE LOW to Output Valid
3.5
ns
t
OELZ
OE LOW to Output Low-Z
[15, 16, 17]
0
ns
t
OEHZ
OE HIGH to Output High-Z
[15, 16, 17]
3.5
ns
Set-up Times
t
AS
Address Set-up before CLK Rise
1.5
ns
t
ALS
ADV/LD Set-up before CLK Rise
1.5
ns
t
WES
WE, BW
[A:B]
Set-up before CLK Rise
1.5
ns
t
CENS
CEN Set-up before CLK Rise
1.5
ns
t
DS
Data Input Set-up before CLK Rise
1.5
ns
t
CES
Chip Enable Set-up before CLK Rise
1.5
ns
Hold Times
t
AH
Address Hold after CLK Rise
0.5
ns
t
ALH
ADV/LD Hold after CLK Rise
0.5
ns
t
WEH
WE, BW
[A:B]
Hold after CLK Rise
0.5
ns
t
CENH
CEN Hold after CLK Rise
0.5
ns
t
DH
Data Input Hold after CLK Rise
0.5
ns
t
CEH
Chip Enable Hold after CLK Rise
0.5
ns
Notes:
12. Timing reference level is 1.5V when V
DDQ
= 3.3V and 1.25V when V
DDQ
= 2.5V.
13. Test conditions shown in (a) of AC Test Loads, unless otherwise noted.
14. This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
minimum initially before a read or write operation
can be initiated.
15. t
CHZ
, t
CLZ
, t
OELZ
, and t
OEHZ
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
16. At any given voltage and temperature, t
OEHZ
is less than t
OELZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve tri-state prior to Low-Z under the same system conditions.
17. This parameter is sampled and not 100% tested.