Switching characteristics – Cypress Perform CY7C1370D User Manual
Page 20
CY7C1370D
CY7C1372D
Document #: 38-05555 Rev. *F
Page 20 of 28
Switching Characteristics
Over the Operating Range
[23, 24]
Parameter
Description
–250
–200
–167
Unit
Min.
Max.
Min.
Max.
Min.
Max.
t
Power
[19]
V
CC
(typical) to the first access read or write
1
1
1
ms
Clock
t
CYC
Clock Cycle Time
4.0
5
6
ns
F
MAX
Maximum Operating Frequency
250
200
167
MHz
t
CH
Clock HIGH
1.7
2.0
2.2
ns
t
CL
Clock LOW
1.7
2.0
2.2
ns
Output Times
t
CO
Data Output Valid After CLK Rise
2.6
3.0
3.4
ns
t
EOV
OE LOW to Output Valid
2.6
3.0
3.4
ns
t
DOH
Data Output Hold After CLK Rise
1.0
1.3
1.3
ns
t
CHZ
Clock to High-Z
[20, 21, 22]
2.6
3.0
3.4
ns
t
CLZ
Clock to Low-Z
[20, 21, 22]
1.0
1.3
1.3
ns
t
EOHZ
OE HIGH to Output High-Z
[20, 21, 22]
2.6
3.0
3.4
ns
t
EOLZ
OE LOW to Output Low-Z
[20, 21, 22]
0
0
0
ns
Set-up Times
t
AS
Address Set-up Before CLK Rise
1.2
1.4
1.5
ns
t
DS
Data Input Set-up Before CLK Rise
1.2
1.4
1.5
ns
t
CENS
CEN Set-up Before CLK Rise
1.2
1.4
1.5
ns
t
WES
WE, BW
x
Set-up Before CLK Rise
1.2
1.4
1.5
ns
t
ALS
ADV/LD Set-up Before CLK Rise
1.2
1.4
1.5
ns
t
CES
Chip Select Set-up
1.2
1.4
1.5
ns
Hold Times
t
AH
Address Hold After CLK Rise
0.3
0.4
0.5
ns
t
DH
Data Input Hold After CLK Rise
0.3
0.4
0.5
ns
t
CENH
CEN Hold After CLK Rise
0.3
0.4
0.5
ns
t
WEH
WE, BW
x
Hold After CLK Rise
0.3
0.4
0.5
ns
t
ALH
ADV/LD Hold after CLK Rise
0.3
0.4
0.5
ns
t
CEH
Chip Select Hold After CLK Rise
0.3
0.4
0.5
ns
Notes:
19. This part has a voltage regulator internally; t
Power
is the time power needs to be supplied above V
DD
minimum initially, before a Read or Write operation can be
initiated.
20. t
CHZ
, t
CLZ
, t
EOLZ
, and t
EOHZ
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
21. At any given voltage and temperature, t
EOHZ
is less than t
EOLZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
22. This parameter is sampled and not 100% tested.
23. Timing reference is 1.5V when V
DDQ
= 3.3V and is 1.25V when V
DDQ
= 2.5V.
24. Test conditions shown in (a) of AC Test Loads unless otherwise noted.