Make Noise MATHS - Manual (Page 18)

Pseudo-VCA with clipping - Thanx to Walker Farrell
Patch audio signal to CH. 1, with RISE and FALL at full CCW, or cycle CH. 1 at audio rate. Take output from
SUM out. Set initial level with CH. 1 panel control. Set CH. 2 panel control full CW to generate a 10v offset.
Audio will start to clip and may become silent. If it's still audible, apply an additional positive offset with CH. 3
panel control until it is just silent. Set CH. 4 panel control to full CCW and apply envelope to Signal IN, or
generate envelope with CH. 4. This patch creates a VCA with asymmetrical clipping in the waveform. It will
work with CV also, but be sure to adjust CV input settings to deal with the large base offset. The INV output
may be more useful in some situations.
Patch Ideas: Digital Signals, Clocks, Gates, Pulses, Events, Timing
Typical Voltage Controlled Pulse/ Clock w/ Voltage Controlled Run/ Stop (Clock, pulse LFO)
Same as above, only the output is taken from EOC or EOR. CH. 1, RISE parameter will more effectively
adjust frequency, and CH. 1 FALL parameter will adjust pulse width. With CH. 4, the opposite is true where
RISE adjust more effectively Width and FALL adjust frequency. In both channels all adjustment to RISE and
FALL parameters will affect frequency. Use CYCLE IN for Run/ Stop control.
Voltage Controlled Pulse Delay Processor
Apply Trigger or Gate to Trigger IN if CH. 1. Take output from End Of Rise. RISE parameter will set delay
and FALL parameter will adjust width of the resulting pulse.
Voltage Controlled Clock Divider Clock signal applied to Trigger IN CH. 1 or 4 is processed by a divisor as
set by RISE parameter. Increasing RISE sets divisor higher, resulting in larger divisions. Fall time will adjust
the width of the resulting clock. If the Width is adjust to be greater the total time of the division the output will
remain “high.”
FLIP-FLOP (1-Bit Memory)
In this patch CH. 1 Trigger IN acts as the “Set” input, and CH. 1 BOTH Control IN acts as the “Reset” input.
Apply Reset signal to CH. 1 BOTH Control IN. Apply Gate or logic signal to CH. 1 Trigger IN. Set RISE to
Full CCW, FALL to Full CW, Vari-Response to Linear. Take “Q” output from EOC. Patch EOC to CH. 4 Signal
to achieve “NOT Q” at the EOC OUT. This patch has a memory limit of about 3 minutes, after which it forgets
the one thing you told it to remember.
Logic Invertor
Apply logic gate to CH. 4 Signal IN. Take output from CH. 4 EOC.
Comparator/Gate Extractor (a new take) Send signal to be compared to CH. 2 IN. Set CH. 3 panel control
into the negative range. Patch SUM out into CH. 1 Signal IN. Set CH. 1 RISE and FALL to 0. Take output
from CH. 1 EOR. Observe signal polarity with CH. 1 UNITY LED. When signal goes slightly positive, EOR
will trip. Use CH. 3 panel control to set the threshold. Some attenuation of CH. 2 may be necessary to find
the right range for a given signal. Use CH. 1 FALL control to make the gates longer. CH. 1 RISE control sets
the length of time the signal must be above the threshold to trip the comparator.