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Timing diagrams – Cypress CY7C1336H User Manual

Page 11

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PRELIMINARY

CY7C1336H

Document #: 001-00210 Rev. *A

Page 11 of 15

Write Cycle Timing

[16, 17]

Note:

17. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW

[A:D]

LOW.

Timing Diagrams

(continued)

tCYC

t

CL

CLK

tADH

tADS

ADDRESS

t

CH

tAH

tAS

A1

tCEH

tCES

High-Z

BURST READ

BURST WRITE

D(A2)

D(A2 + 1)

D(A2 + 1)

D(A1)

D(A3)

D(A3 + 1)

D(A3 + 2)

D(A2 + 3)

A2

A3

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

t

OEHZ

tADVH

tADVS

tWEH

tWES

t

DH

t

DS

t

WEH

t

WES

Byte write signals are ignored for first cycle when
ADSP initiates burst.

ADSC extends burst.

ADV suspends burst.

DON’T CARE

UNDEFINED

ADSP

ADSC

BWE,

BW

[A:D]

GW

CE

ADV

OE

Data in (D)

Data Out (Q)

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