Digilent 410-146P-KIT - Manual (Page 4)

CoolRunner-II Starter Board Reference Manual
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Demonstration Design
The design pre-programmed onto the CPLD contains several functions that can be seen when the
appropriate peripheral modules are inserted into the relevant ports.
In this sample design, the switch Pmod goes in port J8, the PS/2 Pmod goes in port J7,
and the seven-segment display Pmod goes in ports J5 and J6. Of course, the design can be changed
to use different ports.
The CPLD implements both a counter as well as a PS/2 keyboard decoder. The display switches
between the two based on the value of SW4. SW1, 2, and 3 are not used in the design. BTN0 is the
system reset for the design.
When SW4 has the PS/2 decoder selected, the output on the display is the scan code for that letter.
Here are some scan codes, the rest can be found on the Internet.
Keyboard Key Scan Code Keyboard Key Scan Code
F1 05 F5 03
F2 06 F6 0B
F3 04 F7 83
F4 0C F8 0A
Design Recommendations

The regulator provides Vccio of 3.3V, so set the Default I/O Standard appropriately.

Unused I/O should be set to Ground to minimize power.

Input Termination should be set to Keeper to minimize power consumption on any potentially
floating input pins.